ASIC design Lead

Exp: 8-15years experience in ASIC design & integration Description : Understanding the requirement of NoC-NoC connection and the protocol used for the interface. Cleaning-up the Client-based uflow on the RTL front-end checks and delivering to the verification team and SoC team Roles and Responsibilities:

1. Understanding the architecture of NoC topology, bus interface protocol and their

1. Performing lint checks on the RTL and debug using spyglass lint tool.
2. Performing CDC check on the RTL and debug using spyglass CDC tool.
3. Maintaining the proper flow clean RTL on the clearcase tool database.
4. Delivering clock & reset, memory, address map, connectivity check between master & slave and interface details to SoC team for the SoC level validation.