Lead ASIC Design and STA Engineer

Description: This position is for Lead STA engineer who will oversee full chip and/or subsystem level STA convergence from early stages to signoff. Taking part in top level floorplan and clock planning. Work closely with logic design and DFT engineers to define and implement constraints for the various work modes including their optimization of runtime.

• Atleast 7+ years of experience in ASIC timing constraints generation and timing closure.
• Expertise in one or more static timing tools: (Primetime/Tempus and timing eco using Primeclosure/ PT-DMSA).
• Hands on experience in timing constraint analysis and debug using industry standard tool (fishtail).
• Experience in ACIO timing / interface budgeting / process margins / corner definitions / setting up of frequency target with technology scaling.
• Expertise in block level and full chip timing closure
• Familiarity with synthesis, CDC, logic equivalence, DFT.
• Full chip/ sub system level clock tree synthesis and advanced clock tree implementation.
• Experience in ECO generation flow for RTL, pre-physical and post route implementation considering timing, congestion and logic equivalence.
• Automation to improve PPA (power/performance/area) and ensure a high-quality design environment for SOC.
• Proficient in scripting language (TCL/python).
• Hands on experience in reference flows, excellent debugging skills.