Job details
Design Verification Engineer - VLSI/ASIC/FPGA Hardware Experience: 3 - 25 Years Location: Permanent Remote anywhere in the World Contract Length: 6 Months Type: Full time contract (8 hrs/day) Overlap Hours: 4 hrs/day with PST Mandatory Skills
- Overall - 5 years of experience.
- Minimum of 2 years of relevant experience in Hardware Design and/or Hardware Verification.
- ASIC
- VLSI
- FPGA
- SOC
- SystemVerilog development
- Verilog development
- Testbench development and/or verification.
- BS or MS degree in Electrical, Engineering, or related field.
- 3-5 years of proven experience in hardware design development.
- Expertise in HDLs such as Verilog, SystemVerilog, VHDL, and SystemC.
- Expertise in scripting, front-end and verification workflows, and integrations within the hardware design environment.
- Expertise in UVM environments.
- Expertise in Formal Verification.
- Expertise in Lint process and refinement.
- Good communication skills in English.
- Develop, configure, and customize the hardware design platform, utilizing it to generate vital training data for enterprise LLMs.
- Liaise with research teams to translate requirements into actionable data insights, directly impacting our LLMs' performance.
- Uphold the highest standards in coding, debugging, and documentation, ensuring the hardware design solutions are optimized for LLM training and benchmarking.
- Collaborate across teams to identify and prioritize needs, contributing to the LLMs' ability to understand and automate complex processes.
- BS or MS degree in Electrical, Engineering, or related field.
- 3-5 years of proven experience in hardware design development.
- Expertise in HDLs such as Verilog, SystemVerilog, VHDL, and SystemC.
- Expertise in scripting, front-end and verification workflows, and integrations within the hardware design environment.
- Exceptional problem-solving, communication, and collaborative skills.
- Familiarity with ML and AI systems.
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Hiring company
YO IT CONSULTING
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