Verification Lead

Lead Verification Engineer Bristol/Reading I am seeking a dedicated and skilled ASIC Verification Engineer to join our dynamic team for a 6-month fixed contract with a view to go into a permanent position. The Lead Verification Engineer will have expertise in UVM and SystemVerilog to support the development and verification of complex ASIC designs. Responsibilities

• Develop and implement verification environments using UVM methodology
• Create verification plans and test cases to ensure thorough testing of ASIC designs
• Collaborate with design and architecture teams to ensure comprehensive verification coverage
• Perform functional and code coverage analysis to validate the design
• Contribute to verification methodology improvements and best practices

• Bachelor's or Master's degree in Electrical Engineering or Computer Science
• 10+ years industry experience
• Proficiency in SystemVerilog and UVM for ASIC verification
• Solid understanding of digital design fundamentals
• Experience with industry-standard simulation and verification tools
• Strong problem-solving skills and attention to detail
• Excellent communication and teamwork abilities

• Collaborate with the design and architecture teams to understand the ASIC specifications
• Develop and execute comprehensive verification plans to validate the functionality of the ASIC
• Troubleshoot and debug issues found during verification
• Contribute to the ongoing improvement of verification methodologies and processes
• Engage in regular team meetings and knowledge sharing sessions to foster continuous learning and improvement