Senior Silicon Design Verification Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance. THE ROLE: The Unified Memory Controller (UMC) is an IP that delivers into all SOCs that are shipped by AMD's Radeon Technology Group. We deliver discrete graphics, Data Center GPUs and Game Console APUs using a flexible controller design as the base for all our IP. We are looking for a design verification engineer in the Dram Controller IP at AMD's Santa Clara Design Center. You will be working in a fast-paced, complex environment where you will be challenged to provide elegant, robust solutions for increasingly complex features. This is a highly visible position in a growing team. Leadership opportunity is available. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES:

• Work with designers, architects to test plan and execute test plan for various features using various verification methodologies.
• Develop/Enhance UVM testbench components like test-cases, monitors, scoreboards, sequencers, and sequences for new features/projects.
• Drive debug and closure of regression signatures using waveform viewer and output files; and collaborate with the RTL designers and testbench owners to fix bugs.
• Develop quality, timely and cost-effective solutions independently. Contribute to testbench and/or IT infrastructure, helping to build a reliable, scalable, and flexible verification environment.
• Mentoring/Leading junior engineers in the team.

• Strong knowledge in Verilog, System Verilog, and Object-Oriented Programming.
• Experience with UVM or similar Verification Methodology.
• Requires strong Computer Architecture knowledge.
• Strong coding skills in Python/Perl or other industry-standard scripting languages.
• Experience working in a team environment through the ASIC Project lifecycle from Planning to Tape Out.
• Strong communication skills and the ability to work independently as well as in a cross-site team environment.
• Strong OOP programming experience.
• Prior experience with DRAM controllers and DDR phys.
• Experience with formal verification.
• Experience with mentoring and leadership.

• Bachelors or Masters degree in computer engineering/Electrical Engineering.