Design Verification Engineer

Verification Engineer – Senior and Principal levels Bristol, UK This is a fantastic opportunity to help support the continued growth of a Bristol based Chip Team, working on innovative, class leading silicon. My client has opened a small design centre in the bustling City of Bristol. They are developing a novel photonic-electronic architecture that will bring fully homomorphic encryption to the world. The development provides a huge opportunity to become the ubiquitous choice for this new upcoming market across multiple industry sectors. In order to achieve their goal of bringing this technology to the mass market, they are assembling a highly skilled team to build a complex SoC. With the successful recruitment of several Design and Verification Engineers into the team, they continue to build on this and are hiring for 2/3 more Verification Engineers. In this role, you would support the Verification group in defining the verification and validation strategy for the SoC. Working with the SoC Architect and Design team, you would help define and execute the strategy to build a SoC that achieves their technical and commercial goals. To be successful for this role you must have a strong background in SoC verification. UVM experience is a must. You will have:

• A proven track record in SoC verification with exposure to all phases in the flow – requirements collection, methodology and test plans, testbench implementation, coverage closure, documentation etc.
• Deep understanding of modern verification and validation techniques including formal, UVM/OVM/eRM, low power, emulation
• Good knowledge of the SoC design flow from specification to silicon tape-out