physical design STA Engineer
Full time
at Modernize Chip Solutions (MCS)
in
India
Posted on January 25, 2025
Job details
Hands on experience in following : -
- Working knowledge of Synthesis, LEC and STA and concepts behind it.
- Block level synthesis & sub-top/top level timing signoff, generating timing ECOs with hierarchical scope.
- Feedback to RTL design on lint and timing issues from block & sub-top-level STA.
- Experience with Genus, Conformal and Tempus tool is must.
- Proficient in TCL, Python etc.
- Good understanding of multiple clock domain timing analysis, OCV/AOCV/SOCV and clock tree concepts
- Good written and verbal communication skills and aptitude.
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