Field-Programmable Gate Arrays Engineer

In the role of FPGA Developer, you will play a critical role in deploying our electronics in multiple space applications. As a key member of a highly professional and supportive team, you will collaborate with our hardware and software experts to design, develop, and test FPGA logic implementations. By supporting both delivery of our standard products and for custom design projects, your FPGA logic will play critical roles in missions on Low Earth Orbit, in lunar applications, and beyond. Specifically, you will execute the following functions:

• Generate logic projects to support our embedded Q-card platforms:

1. Xilinx Vivado: Zynq, UltraScale+ and Versal
2. Microsemi Libero: ProASIC3 and PolarFire
3. Write physical and timing constraints, meet timings
4. Propose and implement pinouts for new designs

• FPGA logic design

1. Custom IP cores creation
2. Define requirements, interfaces, ports, and parameters
3. VHDL – Verilog coding
4. Verification and simulation
5. Vendor and third-party IP core integration
6. High-Speed examples: PCIe, Gig Ethernet, JESD
7. Low-Speed examples: UART, SPI, I2C
8. Documentation
9. Logic architecture, description, interfaces, clock and reset scheme, register map

• Automated Verification (simulation)

1. Testbench creation, write self check unit tests, regression testing
2. Firmware release support

• FPGA IP Core library maintenance
• FPGA Infrastructure

1. Contribute to put in place a build farm
2. Automate register interfaces
3. Scripting : Project creation, automated pinouts, FPGA bistream generation

• Participate to the logic design and review process
• Support to the test team and customers’ de-bugging

• Coding languages

1. VHDL,
2. Verilog and System Verilog are good assets

• Advanced Verification is an asset (OSSVM, UVM)
• FPGA Physical design and optimisation
• Timing closure
• FPGA Development

1. Xilinx Vivado
2. Microsemi Libero an asset
3. Vivado HLS an asset

• Simulation Tool (one among the list)

1. Modelsim, Questa
2. Active-HDL, Rivera Pro
3. Vivado Simulator

• Good understanding of synchronous design

1. Clocking, pipeline, clock domain crossing
2. Clock enable, reset, back pressure
3. FIFO
4. PLL
5. DSP knowledge is an asset

• Scripting Languages

1. Python, TCL is an asset, Bash is an asset

• Revision Control

1. GIT

• FPGA Interconnect Interfaces like AMBA AXI, AHB
• Debugging in the lab

• Autonomous
• Show initiative
• Rigorous and methodological approaches
• Engaged
• Capacity to take responsibility
• Good analysis skills

• Completed Bachelor’s or Master’s degree in Engineering, Computer Science, or other related area of study
• A minimum of 10 years of experience working with FPGAs
• Must be able to obtain Canadian government security clearance
• Bilingual