ETHOS TECH ONE PTE. LTD. | Sr /IC Design Engineer (Design Verification)

Job Descriptions Develop and Review Test Plan based on IC design specification Develop constrained-Random verification environment for complex DUT Develop/Modify Testbenches using UVM/SystemVerilog for Pre-Silicon IP or SOCs Implement coverage matrix using cover point and assertion Create and debug tests for DUT Resolve bugs with remote designers Requirements Bachelor/Masters Degree in Electrical/Electronics/Computer Engineering with min 1 year of experience Hands-on experience in Silicon/IP verification using SystemVerilog/UVM Strong understanding of verification process from test plan to coverage completion Strong communication and analytical skills Understanding of HDL (Verilog, VHDL) Experience with designing with FPGA using Vivado is a plus #J-18808-Ljbffr