Physical Design Full Chip Layout/Floor Planning
Full time
at L&T Semiconductor Technologies
in
India
Posted on January 15, 2025
Job details
Description: This position is for a senior-level physical design engineer who will work on Floor planning/Bump Planning/ Pin assignments /Feed through/ LFU Optimization/ Work hands-on to solve critical design and execution issues related to physical verification/implementation and sign-off.
- Strong hands-on experience with Chip Level / Sub-chip level floor planning,
- Performing floor-planning and routing studies and implementation at block and full-chip level
- Push down the top-level floorplan and clock to Partition.
- partition, pin assignment, Power planning, IO/Bump Planning , Pad Ring Creation, Die File Creation, RDL Routing, working with Package Team for Optimize the Bumps.
- Closely working with Package team and reaching Die file milestones
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