Senior Staff Engineer - Digital Design

Job Description In your new role you will: Work as architect with system engineers to define IP specifications, architecture & test concept. Specify, rtl design and verify digital circuits in achieving high performance, low power, and efficient implementation for sensor IPs. Perform RTL design and behavioral model coding, Logic Synthesis, Static Timing Analysis, and structural checks as LEC, Spyglass (Linting, CDC & RDC). Execute DFT/power integrity-related activities – Scan Insertion, ATPG & power analysis. Work with Physical designer to achieve timing closure and ECO fixes if required. Conduct design reviews and support in documentation. Support verification engineer to define verification test items. Support in the roadmap formulation for the sensor IPs. Support view generation engineers to verify the correctness of the IPs views. Your Profile You are best equipped for this task if you have: Bachelor/Masters Degree in Electrical Engineering or similar field with a focus on electronics. 8+ years of professional experience in the field of Digital Design with good knowledge of EDA tools (Cadence, Synopsys). Proven track record to formulate digital design architecture and concept & to work together in a team of designers. Proficiency in System Verilog and/or Verilog/VHDL for RTL design and verification tasks. Familiar with the entire digital design flow as in LEC, Spyglass, defining constraints for synthesis, ATPG and primetime analysis. A good understanding of IP development flow, chip integration, timing-analysis, and testability. Knowledge in mixed signal IPs like ADC, PMU, oscillator and temp sensors would be an advantage. Basic Knowledge about Safety and Security standards and applications (e.g. ISO 26262 and ISO 21434, respectively) – would be an advantage. Good English communication and interpersonal skills. Strong analytical and problem-solving skills. #J-18808-Ljbffr