Vhunt4u | Memory Layout Engineer - (TSMC 3nm / 5nm)

We are seeking a highly skilled and motivated Memory Layout Design Engineer to join our offshore development teams. The ideal candidate will have expertise in advanced process nodes (TSMC 3nm & 5nm) and a strong background in layout design for memory technologies. This role involves working on cutting-edge designs for high-performance and low-power applications, contributing to the development of next-generation semiconductor solutions. Role & Responsibilities: Layout Design and Verification:

• Create detailed and optimized physical layouts for memory cells, arrays, and peripheral circuits using tools like Cadence Virtuoso or Synopsys Custom Compiler.
• Perform parasitic extraction and ensure compliance with DRC (Design Rule Check) and LVS (Layout Versus Schematic) rules.

• Work closely with circuit designers to ensure the layout meets electrical and performance specifications, such as timing, power, and area (PPA).
• Provide feedback on circuit designs to improve layout efficiency.

• Understand and implement layout requirements for advanced nodes (3nm, 5nm, 7nm), including FinFET architecture and challenges such as variability and manufacturability.
• Address process-dependent effects like electromigration (EM), IR drop, and self-heating.

• Utilize EDA tools for layout design, simulation, and verification, ensuring compliance with foundry-specific PDKs (Process Design Kits).
• Automate repetitive tasks and improve workflow efficiency using scripting (e.g., Python, SKILL).

• Optimize layouts for yield enhancement and manufacturing robustness.
• Perform debugging of silicon failures and identify layout-related issues.