Verification Engineer

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field.
• 5+ years ASIC design, verification, or related work experience.

• Familiarity with automotive safety standards (ASIL) and ISO26262.
• Past experience with automotive safety design and tool methodologies.
• Experience in design, testing and verification in hardware and software on SoCs and SoC Methodologies for verifying complex units on SoC using industry standard tools and technologies.
• Proficient in developing unit and SoC level test benches using VMM/OVM/UVM.
• Constrained random functional verification environment in System Verilog.
• Experience in Gate Level Simulation (GLS) verification flow for SoC verification.
• Experience of pre and post-silicon verification testflow and automated test benches.
• Strong knowledge of test-plan generation, coverage analysis transaction level modeling, pseudo and constrained random techniques, assertion based and formal verification techniques with System Verilog.
• Verilog, C/C++, System C, Java, TCL/Perl/shell-scripting required.
• Building and leading verification teams is a plus.
• RTL design and front end design flow experience.
• Formal verification methodology.
• Excellent communication skills.