Senior Design Verification Engineer - PCI-e

Responsibilities :- Design and develop robust verification plans for intricate digital designs, focusing on PCIe interfaces with Gen 1/3/4/5 protocols (Logical PHY, LTSSM, DLL & TL).- Independently code UVM/SV-based components, relevant logic, and test cases.- Conduct in-depth debugging of test failures to identify root causes in complex design scenarios.- Demonstrate strong knowledge in PCIe specifications and capabilities.- Utilize debugging skills with both log files and waveforms to effectively troubleshoot issues.- Contribute to writing constraints, assertions, and functional coverage using SystemVerilog.- Quickly grasp and understand complex test benches.- Familiarity with Register Abstraction Layer (RAL) concepts is a plus.Qualifications :- Minimum of 6+ to 8+ years of experience in design verification, with a proven track record in PCIe verification.- Hands-on proficiency in SystemVerilog (SV) and UVM methodologies.- Excellent debugging skills with a keen eye for detail.- Strong analytical and problem-solving abilities.- Effective communication and collaboration skills.- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (or equivalent work experience).- Prior experience with third-party test suites is a valuable asset (ref:hirist.tech)