DFT Director - Design for Testability (DFT)

Mirafra Technologies Hiring Position : DFT Director – Design for Testability (DFT) Location : Bangalore Experience Level : 14+ years in semiconductor design, with extensive expertise in DFT methodologies About the Role We are seeking a seasoned leader to spearhead our Design for Testability (DFT) division. The DFT Director will play a pivotal role in defining, developing, and growing our DFT capabilities, ensuring we remain at the forefront of semiconductor design services. This individual will oversee project delivery, team development, and client engagement, driving excellence and innovation in DFT methodologies. Key Responsibilities

• Leadership :Define the vision, strategy, and roadmap for the DFT division aligned with organizational goals.
• Establish thought leadership in the domain through white papers, industry events, and partnerships.
• Technical Excellence :Oversee the implementation of cutting-edge DFT techniques, including scan insertion, ATPG, MBIST, LBIST, and boundary scan (JTAG).
• Ensure projects meet or exceed client expectations
• Stay updated with emerging trends in DFT and test automation.
• Business Development :Collaborate with sales teams to identify and pursue new business opportunities.
• Engage with clients to understand their DFT needs and propose tailored solutions.
• Contribute to revenue growth by expanding the division's client portfolio and scope of offerings.
• Team Building and Mentorship :Build and nurture a team of high-performing DFT engineers.
• Conduct training sessions to upskill team members and ensure technical excellence.
• Foster a culture of collaboration, continuous learning, and innovation.
• Project Management :Oversee the end-to-end delivery of DFT projects, ensuring adherence to timelines, budgets, and quality standards.
• Resolve escalations and technical challenges effectively.

• Bachelor’s/Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 14+ years of experience in semiconductor design, with at least 5 years in a leadership role focusing on DFT.
• Deep expertise in DFT methodologies, including:Scan-based testing, ATPG, and fault simulation.
• Built-In Self-Test (BIST) techniques.
• Test compression and low-power testing.
• DFT for hierarchical and multi-die designs.
• Proven track record of successful client engagements and project delivery.
• Strong leadership, communication, and business acumen.
• Familiarity with industry-standard tools such as Mentor Tessent Synopsys Tetramax, , or Cadence Modus.

• Experience with multi-site and global team management.
• Hands-on experience with post-silicon debug and ATE testing.
• Strong understanding of emerging trends in AI-driven test automation and DFT for advanced nodes (e.g., 5nm, 3nm).