ASIC Digital Design, Staff Engineer

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.You Are: An enthusiastic and detail-oriented ASIC Digital Engineer with a passion for cutting-edge technology and a penchant for solving complex problems. You thrive in a collaborative environment and are adept at translating high-level requirements into robust and efficient designs. Your expertise, coupled with your strong understanding of digital design and verification methodologies, makes you an invaluable asset to any project. You are proactive, with excellent communication skills that enable you to work effectively with cross-functional teams. Your ability to adapt quickly to new challenges and technologies ensures that you remain at the forefront of industry advancements.What You'll Be Doing:Designing digital IP for ASICs, focusing on PCIe and CXL protocols;Performing RTL coding and simulation to optimize design performance and efficiency;Developing and executing test plans to ensure comprehensive coverage of all design aspects;Collaborating with cross-functional teams to ensure thorough testing and validation of designs;Conducting design and verification reviews and providing constructive feedback to improve overall quality and functionality;Debugging and resolving complex design and verification issues;Documenting design specifications, test plans, and verification reports.The Impact You Will Have:Contributing to the successful delivery of high-performance silicon chips that power next-generation technology;Enhancing the reliability and performance of Synopsys products through rigorous design and verification;Driving innovation by developing cutting-edge solutions for PCIe and CXL protocols;Strengthening Synopsys' reputation as a leader in the semiconductor industry;Improving the efficiency and effectiveness of the design and verification process;Supporting the continuous improvement of design methodologies and best practices.What You'll Need:Proficiency in digital design and verification methodologies.Experience with RTL coding using Verilog or VHDL.Strong understanding of digital design principles, including timing analysis and optimization.Expertise in using advanced verification techniques, including UVM.Familiarity with scripting languages such as Python or Perl for automation.Strong knowledge of PCIe and CXL protocols desired but not essential.MSc or PhD in Electrical Engineering or Computer Science;6+ years of relevant experience.Who You Are:An analytical thinker with a keen eye for detail.A proactive problem-solver who can navigate complex challenges.An excellent communicator who can articulate technical concepts to diverse audiences.A collaborative team player who thrives in a dynamic environment.A continuous learner who stays updated with industry trends and advancements.A results-driven professional committed to delivering high-quality work.The Team You'll Be Part Of: You will join a dedicated team of engineers focused on the design and verification of high-performance digital ASICs. Our team is committed to innovation, quality, and excellence, working collaboratively to push the boundaries of technology. We value continuous learning and professional growth, providing ample opportunities for development and advancement.Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.Inclusion and Diversity: Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

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