Physical Design (PD) Engineers (Lisbon, Porto, Fundão)
Job details
Capgemini Engineering
At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world's most innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the same.
Your Role
Overseeing all aspects of Physical Design at either the full chip or block level, particularly in highly advanced technology nodes (10nm and below).
Engaging deeply in floorplanning, partitioning/budgeting, power mesh distribution, clock tree planning and analysis, Scan re-ordering, placement, CTS, and place and route.
Handling all relevant activities related to timing analysis, ensuring closure through sign-off, including SI/noise, and performing ECO tasks (both functional and timing).
Leading validation/qualification tasks such as Formal Verification, EM/IR, DRC, LVS, Antenna, and ERC analysis and fixes.
Contributing to the overall development and implementation of Low Power solutions.
Developing/enhancing timing-related scripts for tasks like clock skew analysis, critical path analysis, various IO interfaces, and constraints partitioning/budgeting (from top-level to block level).
Successfully completing multiple design cycles of high complexity with minimal supervision.
Your Profile
BSC/MSC in Electrical/Computer Engineering.
More than 5 years of experience in challenging RTL2GDSII work conducted on 10nm or below nodes, with designs containing 500k - 1million+ instances.
Proficiency in using PnR and timing analysis CAD tools from Synopsys and/or Cadence.
Good understanding of synthesis flow, DFT scan/coverage, and optimization.
Excellent floorplan, power plan, CTS, place, route, and timing closure skills.
Proficiency in Perl/TCL/Python scripting and Makefile.
Expertise in timing STA/PTSI - signal integrity closure, and ECO generation/implementation.
Strong EM/IR, DRC, LVS, ERC analysis, and fixing capabilities.
Experience with sign-off tape-out closure work.
Any experience in top-level activities like floor planning, pin assignment, and tape-out is advantageous.
What you'll love about working here
Join a multicultural and inclusive team environment.
Enjoy a supportive atmosphere promoting work-life balance.
Hybrid work.
Your career growth is central to our mission. Our array of career growth programs and diverse professionals are crafted to support you in exploring a world of opportunities.
Access valuable training and certifications in cutting-edge technologies.
Engage in exciting national and international projects.
Health and life insurance.
Referral program with bonuses for talent recommendations.
Great office locations.
ABOUT CAPGEMINI
Choosing Capgemini means choosing a company where you will be empowered to shape your career in the way you'd like, where you'll be supported and inspired by a collaborative community of colleagues around the world, and where you'll be able to reimagine what's possible. Join us and help the world's leading organizations unlock the value of technology and build a more sustainable, more inclusive world.
#J-18808-Ljbffr Engenharia e tecnologia
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