Test Validation Engineer

Job Description and Requirements -Must have BSEE and 2+yrs exp or MSEE with ~1 yrs experience -Work on projects or processes within area of responsibility in defined components -Productive professional who applies practical knowledge of organization policies & procedures to resolve variety of issues within functional area. -Sound fundamentals in Digital electronics. HDL Languages coding experience preferably in Verilog/VHDL/System Verilog -Understanding & experience in Formal concepts: FPV (Formal Property Verification), Coverage, Simulation, writing SVA -Has familiarity with scripting languages & developed some automation in previous projects preferably in: Python/Perl -Writing testplans/testcases/Run benchmark designs to validate complex tool features in Formal methodology -Reviewing, resolving and maintenance of daily regressions & benchmark failures -Diagnosis, troubleshooting, Automation testing of EDA tools internally Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.