PNR lead

Technical Skills:

• Should be able to handle Full chip PnR (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage design Deep understanding of the concepts related to synthesis, place route, CTS, timing convergence, IR/EM checks and signoff DRC/LVS closure Responsible for independent planning and execution of all aspects of physical design including floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM.
• Must have participated in all stages of the design (floor planning, placement, CTS, routing, physical verification, IREM).
• Well versed with the timing closure (STA), timing closure methodologies.
• Good Understanding of DRC, LVS,ERC and PERC rule files for lower tech node layout verification.
• Experience in lower tech node (<7nm).
• Good automation skills in PERL, TCL and EDA tool-specific scripting.
• Able to take complete ownership for Block/sub-system for complete execution cycle.
• Out of box thinking to meet tighter PPA requirements

• BE/BTECH/MTECH in EE/ECE with proven experience in ASIC Physical Design.
• Detailed knowledge of EDA tools and flows, Fusion compiler based RTL2GDS flow is desired
• Experience – 7+ Yrs