Senior ASIC RTL Design
Full time
at Mulya Technologies
in
Online
Posted on September 4, 2024
Job details
- Name of position: Senior ASIC RTL Design
- Number of Positions: 2
- Location of Position: Hyderabad/Bangalore/Chennai
- Mode of work: In office [5 Days] [For Bangalore/Chennai it will be remote]
- Required Experience level: 8+ years
- Required Key Skills: RTL Logic Design, Interface Protocols [PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, etc.]
- Required Qualifications: BTech/MTech Note:
- Hyderabad will be the first priority as location.
- For Bangalore/Chennai it will be remote as they have office in Hyderabad
- Help develop the design and implementation of SoCs.
- Micro-architecture design, RTL coding, synthesis, timing closure, and documentation of various RTL blocks;
- Top-level and block-level performance, bandwidth, and power optimization;
- Work with FPGA engineers to perform early prototyping; and
- Support test program development, chip validation, and chip life until production maturity.
- Collaboration with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams throughout various stages of ASIC development.
- 8+ years of experience in RTL logic design , verification, synthesis, and timing optimization;
- Proficient in writing clear, implementable micro-architecture specifications;
- Expertise in writing efficient RTL code in Verilog and SoC integration
- Good understanding of assertions, coverage analysis, RTL synthesis, and timing closure;
- Should have worked on interface protocols like PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, etc .
- Experience in design bringing up and debugging on FPGA-based emulation platforms like HAPS, and Veloce.
- Fluency with scripting languages (e.g., Perl, Python);
- Must have gone through at least one tape out.
- Preferred: Silicon bring-up and debug experience
- Experience in working with repository management tools like Bitbucket/ Jenkins and bug-tracking tools like JIRA.
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