Senior Design Verification Engineer

Job Title: ASIC DV LeadHi Applicants!!!Hiring for Job in a Reputed Organization (Leading Product Based Company)Here is a Gateway to it, through ALP Consulting.Recruiting for Verification EngineerEmployment Type: PermanentSkills Required: Design Verification,Perl Programming,Verilog,Test Bench,Functional Verification,SystemVerilog,Scripting LanguagesJob Description for Verification EngineerLooking for an experienced senior verification engineer with > 7 years of experience in ASIC/SOC/IP/block level functional verification using system verilog/UVM.The ideal candidate will have strong command of UVM, advanced UVM and system verilog.Develop a comprehensive test plan, complete test-bench and robust verification environment including interface agents and scoreboard in UVM.possess deep knowledge of at least one industry-standard protocol such as Ethernet, PCIe, DDR, USB, NVMe or similar.Strong debugging skills to address TB issues quickly and test failures.Take responsibility for verification closure by addressing coverage and managing bug reports.proficiency in using industry standard verification tools such as Questa, VCS or ModelSim.Experience with scripting languages like python, perl or TCL for automation tasks.Manage a team of 6 to 7 Engg, Interact with the customer on the tasks and status updates.Experience: 7 to 15 years of experienceSalary: As per Market StandardsNotice period: 60 DaysJob Location: Bangalore, NoidaNote: Immediate joiners or 30 Days' Notice Period will be Prioritized. PRB