Principal Engineer, DFT (Design-for-Testability)

Role - Principal Engineer,(Design-for-Testability)Stream - Customer Focused Product Development for Mobility, Industrial, Energy & TelecomReporting To - Chief Development Officer / Global Head of EngineeringLocation -BengaluruCOMPANY DESCRIPTIONL&T Semiconductor Technologies (LTSCT), a fully owned subsidiary of L&T, is the first major Indian Semiconductor product company - a fabless company for designing & delivering Smart Devices for Global Customers. A company that provides Semiconductor Devices and Technology partnerships by helping customers realise energy efficient, high-performance systems to benefit from data, electrification and software defined technology trends.Harnessing the engineering mastery of L&T, LTSCT is forging a path to a world-class semiconductor ecosystem rooted in India. We aim to rewrite the rules of cutting-edge technology through relentless innovation to foster a vibrant culture of ingenuity, fuelling progress on every chip.We have a presence in four prominent geographies i.e. US, Europe, Japan and India, with offices in Austin, Munich, London, Tokyo, Bangalore and Chennai. JOB DESCRIPTION LTSCT's Chief Development Organization and Global Engineering team is a central engineering organization responsible for developing and delivering Systems-on-a-Chip (SoCs) for LTSCT's Automotive, Industrial, Energy and Telecom infra business lines. The team is challenged to produce industry-leading solutions covering very cost-sensitive, low power devices to highly integrated, high performance, multi-domain devices compliant with the latest automotive and industrial safety and security standards. AREAS OF RESPONSIBILITY:Design for Test (DFT) engineering organization at L&T Semiconductor Technologies (LTSCT) works on groundbreaking methods & technologies for innovations in DFT architecture, verification & post silicon bring up of state-of-the-art semiconductor chips like system on a chip (SOCs) built on the latest semiconductor technology nodes. Responsibilities: You will drive the DFT activities to implement the DFT structures on the complex SOCs, verify the DFT operations of the chips & support the silicon bring up team using the DFT vectors on the ATE machines. You will mentor Junior team members for DFT implementation on SOCs. You will own & implement the following activities on the SOCs.MBIST structure insertion to the design.Compressor based Scan chain insertion.BSCAN structure insertion based on the IEEE 1149.1 & 1149.6 standards.Logic BIST implementation for the Self-test capabilityAnalog BIST implementation for selected analog blocks like PLLs, ADC & DACs.IOBist methods implementation for IO structures of the SOCs.You will work with cross-functional teams like design, physical design, verification teams to deliver the DFT solutions to the SOCs in predefined schedule. QualificationsMust have master's degree in the area of computer or electrical engineering from a reputed university.Must have at least 12-15 years of hands-on experience in DFT implementation, Verification & Debug of complex large SOCs using Industry standard methods & tools.Must have experience with Streaming Scan network (SSN) based DFT technology, implemented on SOCs built on latest semiconductor nodes like FINFET technologies.Good exposure to industry standard Physical design tools (place & route) & methods, timing analysis using static timing analysis (STA) tools.Must have very good written & oral communication skills, ability to motivate team members to do innovation in DFT architecture & related areas.Must be familiar with DFT related industry standards like IEEE 1149.1, IEEE 1500 etc.Must have experience in scripting languages like Perl, Tcl, Shell PRB