RTL Principal Design Engineer

Design & synthesize for a complex SerDes IPs in various technology nodes (> 100G rates)Work with Analog design teams to co-develop algorithms, feedback design loops as well as high speed critical digital circuitsGood understanding of working with signal processing IPs in terms of knowing calibrations, PLLs, dividers, FIFO design and reset distributionProficient in RTL coding, DSP datapath designs as well as control FSM ensuring timing closures at 2GHz and above at lower geometry nodesVery good in understanding and defining timing constraints and critical high speed path timing closure working with BE teamsGeneral flow understanding of various stages and steps involved in Serdes design flow will be a huge plus including AMS modelling and SV RNM verification.Good knowledge of functional (analog BIST, eye-surf) and structural DFT (Bscan, Scan etc..) for high speed PHY IPs will be a plus.Work closely with analog and validation teams to bring up silicon and fine tune and debug performance issues at high speedStrong knowledge on complete Implementation flows and rigorous checks before delivery to other teams or customers ex- LINT, SDC, CDC, DFT, Low power and trial PnR PRB