ASIC RTL Design Engineer
تفاصيل الوظيفة
• MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital design • Experience with Verilog and system Verilog • Experience with VCS, Verdi or other industry standard tools • Experience with pre-layout simulation and post-layout simulation • Understanding of the design flow. Ability to work with the backend team • Familiarity with AMBA APB AXI Protocol • Familiarity with RISC/Arm or other core architectures • Ability to create innovative architecture and solutions to customer requirements
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