Senior SoC Design Manager

DFT Lead / Manager / Senior Manager Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore A US based well-funded product-based startup looking for Highly talented Senior SOCManager / SoC Manager / Lead for the following roles. SoC Chip Lead / Manager / Senior Manager defines SoC architecture & solutions enabling the next generation SoC product for company's Server based product line. In this role you will collaborate with cross-functional teams, including hardware, software, verification, physical design engineers, to define and implement SoC architectures that meet the product requirements. We are seeking highly experience individuals who have a passion for innovation and are excited about the opportunity to create products from scratch. The key responsibilities for this role include, but are not limited to: Key Responsibilities: Collaborate with cross-functional teams to define and architect SoCs for HPC platform Conduct feasibility studies and performance analysis to determine optimal SoC architectures, subsystems, and interfaces. Develop and review specifications, microarchitecture, and system-level design documentation for SoCs. Writing SoC level constraints for implementation flow Lead a team of SoC engineers for successful tapeout and bringup Work closely with Architects, DV, DFT, PD, SW teams to ensure successful integration and functionality of the SoCs. Drive innovation by exploring new technologies, methodologies, and industry trends relevant to SoC design. Optimize SoC designs for power, performance, area, and other key metrics. Collaborate with customers and partners to understand their requirements and provide SoC solutions that meet their needs. Provide technical guidance and mentorship to junior members of the team. Qualifications: B. Tech / M. Tech in ECE or CS or equivalent degree from premier institutes with 12-18 years of experience Proven experience in SoC architecture and design using PCIe/CXL, D2D/UCIe, NVMe, DDR5, LPDDR5X Expertise in one or more application domains, such as Cache Controllers, NoC In depth understanding of modeling, workloads, SoC benchmarks and PPA tradeoffs Hands on experience with Verilog/SystemVerilog for design Strong understanding of hardware and software interactions in SoCs. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"